In order to reduce on-chip interconnect latency caused by large wiring resistance, it is necessary to insert repeaters (either inverters or buffer amplifiers) periodically along an interconnect wire. Even with inserted repeaters, interconnect latency increases with LSI process scaling and degrades the performance of sophisticated LSIs. This patented technology allows for control of repeaters so that data in the data line is automatically compressed/decompressed with the transmission of signals along the control line.
First independent claim:
1. In an integrated circuit, an interconnect circuit for transmitting data signals, said interconnect circuit comprising:
a data line transmitting said data signals in said integrated circuit; and
a congestion line transmitting congestion signals;
wherein said data line comprises a plurality of data driving circuits which selectively interrupt and reestablish transmission of said data signals responsive to said congestion signals and wherein said plurality of data driving circuits store said data signals temporary when said transmission of said data signals is interrupted.
